BQ4285EP【PDF 31/31 页】IC RTC W/114X8 NVSRAM 24-DIP

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Sheet目录1990

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Control/Status Registers

The four control/status registers of the bq4285E/L are

accessible regardless of the status of the update cycle

(see Table 4).

Register A

The frequency of the square-wave and the periodic

event rate.

Oscillator operation.

Status of the update cycle.

RS0–RS3 - Frequency Select

These bits select one of the 13 frequencies for the SQW out-

put and the periodic interrupt rate, as shown in Table 3.

OS0–OS2 - Oscillator Control

These three bits control the state of the oscillator and di-

vider stages. A pattern of 010 enables RTC operation by

turning on the oscillator and enabling the frequency di-

vider. A pattern of 011 behaves as 010 but additionally

transforms register C into a read/write register. This al-

lows the 32.768kHz output on the square wave pin to be

turned on. A pattern of 11X turns the oscillator on, but

keeps the frequency divider disabled. When 010 is writ-

ten, the RTC begins its first update after 500ms.

UIP - Update Cycle Status

This read-only bit is set prior to the update cycle. When

UIP equals 1, an RTC update cycle may be in progress.

UIP is cleared at the end of each update cycle. This bit

is also cleared when the update transfer inhibit (UTI)

bit in register B is 1.

Register B

Update cycle transfer operation

Square-wave output

Interrupt events

Daylight saving adjustment

Clock and calendar data formats

All bits of register B are read/write.

bq4285E/L

76543210

----

RS3

RS2

RS1

RS0

76543210

OS2

OS1

OS0

----

Register A Bits

76543210

UIP

OS2

OS1

OS0

RS3

RS2

RS1

RS0

76543210

UIP

-------

Register B Bits

7654

210

UTI

PIE

AIE

UIE SQWE

DSE

Reg.

Loc.

(Hex) Read Write

Bit Name and State on Reset

7 (MSB)

0 (LSB)

Yes

UIP

OS2

OS1

OS0 na

RS3

RS2

RS1

RS0

Yes

UTI

PIE

AIE

UIE

SQWE

DSE na

Yes

INTF

32KE na

Yes

VRT

-0-0-

0-0-0

Notes:

na = not affected.

Except bit 7.

Read/write only when OSC2–OSC0 in register A is 011 (binary).

Table 4. Control/Status Registers

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